ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
Classes
architecture.memory_port Namespace Reference

Classes

class  MemoryPortType
 
class  DataDirection
 
class  MemoryPort
 Single port of a MemoryInstance. More...
 
class  PortAllocation
 Port allocation for a single memory instance. More...