ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
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Single port of a MemoryInstance. More...
Public Member Functions | |
def | __init__ (self, str port_name, MemoryPortType type, int bandwidth_min, int bandwidth_max, int|None port_id=None) |
Collect all the physical memory port related information here. More... | |
def | add_port_function (self, OperandDirection operand_level_direction) |
def | port_is_shared_by_two_input_operands (self) |
def | __str__ (self) |
def | __repr__ (self) |
bool | __eq__ (self, Any other) |
def | __hash__ (self) |
Public Attributes | |
name | |
bw_min | |
bw_max | |
type | |
port_id | |
Static Public Attributes | |
int | port_id_counter = 0 |
Single port of a MemoryInstance.
def __init__ | ( | self, | |
str | port_name, | ||
MemoryPortType | type, | ||
int | bandwidth_min, | ||
int | bandwidth_max, | ||
int | None | port_id = None |
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) |
Collect all the physical memory port related information here.
port_name | |
bandwidth_min | bit/cc |
bandwidth_max | bit/cc |
type | read_only (read), write_only (write), read_write (read_write) |
port_id | port index per memory |
bool __eq__ | ( | self, | |
Any | other | ||
) |
def __hash__ | ( | self | ) |
def __repr__ | ( | self | ) |
def __str__ | ( | self | ) |
def add_port_function | ( | self, | |
OperandDirection | operand_level_direction | ||
) |
def port_is_shared_by_two_input_operands | ( | self | ) |
bw_max |
bw_min |
name |
port_id |
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static |
type |