- Generated by
1.9.1
|
ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
|
Class that collects all the data transfer rate information for each DTL (data transfer link). More...
Public Member Functions | |
| def | __init__ (self, int|float real_cycle, int|float data_in_charge, int|float mem_bw, LayerOperand layer_op, int mem_lv, DataDirection mov_dir) |
| def | __str__ (self) |
| def | __repr__ (self) |
Public Attributes | |
| real_cycle | |
| data_in_charge | |
| one-period data transfer amount (bit) More... | |
| mem_bw | |
| bit/cycle More... | |
| served_op_lv_dir | |
Class that collects all the data transfer rate information for each DTL (data transfer link).
| def __init__ | ( | self, | |
| int | float | real_cycle, | ||
| int | float | data_in_charge, | ||
| int | float | mem_bw, | ||
| LayerOperand | layer_op, | ||
| int | mem_lv, | ||
| DataDirection | mov_dir | ||
| ) |
| real_cycle | The actual number of cycles used for transferring the amount of data, depended on the memory bw and the data amount to be transferred at that memory level |
| data_in_charge | One-period data transfer amount (bit) |
| mem_bw | Unit: bit/cycle |
| def __repr__ | ( | self | ) |
| def __str__ | ( | self | ) |
| data_in_charge |
one-period data transfer amount (bit)
| mem_bw |
bit/cycle
| real_cycle |
| served_op_lv_dir |
1.9.1