ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
Classes
zigzag.cost_model.port_activity Namespace Reference

Classes

class  PortActivity
 Class that collects all the data transfer rate (periodic) information for each DTL (data transfer link). More...
 
class  PortBeginOrEndActivity
 Class that collects all the data transfer rate information for each DTL (data transfer link). More...