ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
PortBeginOrEndActivity Member List

This is the complete list of members for PortBeginOrEndActivity, including all inherited members.

__init__(self, int|float real_cycle, int|float data_in_charge, int|float mem_bw, LayerOperand layer_op, int mem_lv, DataDirection mov_dir)PortBeginOrEndActivity
__repr__(self)PortBeginOrEndActivity
__str__(self)PortBeginOrEndActivity
data_in_chargePortBeginOrEndActivity
mem_bwPortBeginOrEndActivity
real_cyclePortBeginOrEndActivity
served_op_lv_dirPortBeginOrEndActivity