ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
MemoryPort Member List

This is the complete list of members for MemoryPort, including all inherited members.

__eq__(self, Any other)MemoryPort
__hash__(self)MemoryPort
__init__(self, str port_name, MemoryPortType type, int bandwidth_min, int bandwidth_max, int|None port_id=None)MemoryPort
__repr__(self)MemoryPort
__str__(self)MemoryPort
add_port_function(self, OperandDirection operand_level_direction)MemoryPort
bw_maxMemoryPort
bw_minMemoryPort
nameMemoryPort
port_idMemoryPort
port_id_counterMemoryPortstatic
port_is_shared_by_two_input_operands(self)MemoryPort
typeMemoryPort