ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
ImcArray Class Reference

definition of an Analog/Digital In-SRAM-Computing (A/DIMC) core constraint: – activation precision must be in the power of 2. More...

Inheritance diagram for ImcArray:
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Public Member Functions

def __init__ (self, bool is_analog_imc, int bit_serial_precision, list[int] input_precision, int adc_resolution, int cells_size, float|None cells_area, dict[OADimension, int] dimension_sizes, bool auto_cost_extraction=False)
 
tuple[float, float, float] get_adc_cost (self)
 single ADC and analog accumulation cost calculation More...
 
tuple[float, float, float] get_dac_cost (self)
 single DAC cost calculation More...
 
def get_area (self)
 get area of IMC macros (cells, mults, adders, adders_pv, accumulators. More...
 
def get_tclk (self)
 get clock cycle time of imc macros (worst path: dacs -> mults -> adcs -> adders -> accumulators) More...
 
dict[str, float] get_peak_energy_single_cycle (self)
 macro-level one-cycle energy of imc arrays (fully utilization, no weight updating) (components: cells, mults, adders, adders_pv, accumulators. More...
 
tuple[float, float, float] get_macro_level_peak_performance (self)
 macro-level peak performance of imc arrays (fully utilization, no weight updating) More...
 
dict[str, float] get_energy_for_a_layer (self, LayerNode layer, Mapping mapping)
 
def __jsonrepr__ (self)
 

Public Attributes

 adc_resolution
 
 bit_serial_precision
 
 cells_w_cost
 
 area_breakdown
 
 area
 
 tclk_breakdown
 
 tclk
 
 mapped_rows_total_per_macro
 
 energy_breakdown
 
 energy
 

Detailed Description

definition of an Analog/Digital In-SRAM-Computing (A/DIMC) core constraint: – activation precision must be in the power of 2.

– bit_serial_precision must be in the power of 2.

Constructor & Destructor Documentation

◆ __init__()

def __init__ (   self,
bool  is_analog_imc,
int  bit_serial_precision,
list[int]  input_precision,
int  adc_resolution,
int  cells_size,
float | None  cells_area,
dict[OADimension, int]  dimension_sizes,
bool   auto_cost_extraction = False 
)
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Member Function Documentation

◆ __jsonrepr__()

def __jsonrepr__ (   self)
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◆ get_adc_cost()

tuple[float, float, float] get_adc_cost (   self)

single ADC and analog accumulation cost calculation

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◆ get_area()

def get_area (   self)

get area of IMC macros (cells, mults, adders, adders_pv, accumulators.

Exclude input/output regs)

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◆ get_dac_cost()

tuple[float, float, float] get_dac_cost (   self)

single DAC cost calculation

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◆ get_energy_for_a_layer()

dict[str, float] get_energy_for_a_layer (   self,
LayerNode  layer,
Mapping  mapping 
)
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◆ get_macro_level_peak_performance()

tuple[float, float, float] get_macro_level_peak_performance (   self)

macro-level peak performance of imc arrays (fully utilization, no weight updating)

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◆ get_peak_energy_single_cycle()

dict[str, float] get_peak_energy_single_cycle (   self)

macro-level one-cycle energy of imc arrays (fully utilization, no weight updating) (components: cells, mults, adders, adders_pv, accumulators.

Not include input/output regs)

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◆ get_tclk()

def get_tclk (   self)

get clock cycle time of imc macros (worst path: dacs -> mults -> adcs -> adders -> accumulators)

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Member Data Documentation

◆ adc_resolution

adc_resolution

◆ area

area

◆ area_breakdown

area_breakdown

◆ bit_serial_precision

bit_serial_precision

◆ cells_w_cost

cells_w_cost

◆ energy

energy

◆ energy_breakdown

energy_breakdown

◆ mapped_rows_total_per_macro

mapped_rows_total_per_macro

◆ tclk

tclk

◆ tclk_breakdown

tclk_breakdown

The documentation for this class was generated from the following file: