ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
MemoryInstance Class Reference

A single instance within the memory hierarchy, without information about connectivity. More...

Public Member Functions

def __init__ (self, str name, int size, float r_cost=0, float w_cost=0, float area=0, int r_port=1, int w_port=1, int rw_port=0, int latency=1, tuple[MemoryPort,...] ports=tuple(), str mem_type="sram", bool auto_cost_extraction=False, bool double_buffering_support=False, int shared_memory_group_id=-1)
 Collect all the basic information of a physical memory module. More...
 
None update_size (self, int new_size)
 Update the memory size of this instance. More...
 
def __jsonrepr__ (self)
 JSON Representation of this class to save it to a json file. More...
 
bool __eq__ (self, object other)
 
def has_same_performance (self, "MemoryInstance" other)
 Wether using this instance will result in the same estimations as using the other instance. More...
 
def __hash__ (self)
 
def __str__ (self)
 
def __repr__ (self)
 

Public Attributes

 name
 
 size
 
 r_cost
 
 w_cost
 
 area
 
 latency
 
 ports
 
 double_buffering_support
 
 shared_memory_group_id
 

Detailed Description

A single instance within the memory hierarchy, without information about connectivity.

Constructor & Destructor Documentation

◆ __init__()

def __init__ (   self,
str  name,
int  size,
float   r_cost = 0,
float   w_cost = 0,
float   area = 0,
int   r_port = 1,
int   w_port = 1,
int   rw_port = 0,
int   latency = 1,
tuple[MemoryPort, ...]   ports = tuple(),
str   mem_type = "sram",
bool   auto_cost_extraction = False,
bool   double_buffering_support = False,
int   shared_memory_group_id = -1 
)

Collect all the basic information of a physical memory module.

Parameters
namememory module name, e.g. 'SRAM_512KB_BW_16b', 'I_RF'.
sizetotal memory capacity (unit: bit).
r_bw/w_bwmemory bandwidth (or word length) (unit: bit/cycle).
r_cost/w_costmemory unit data access energy (unit: pJ/access).
areamemory area (unit can be whatever user-defined unit).
latencymemory access latency (unit: number of cycles).
portstuple of MemoryPort instances.
mem_type(str): The type of memory. Used for CACTI cost extraction.
auto_cost_extraction(bool): Automatically extract the read cost, write cost and area using CACTI.
double_buffering_support(bool): Support for double buffering on this memory instance.
shared_memory_group_idused to indicate whether two MemoryInstance instances represent the same, shared memory between two cores (feature used in Stream).

Member Function Documentation

◆ __eq__()

bool __eq__ (   self,
object  other 
)

◆ __hash__()

def __hash__ (   self)

◆ __jsonrepr__()

def __jsonrepr__ (   self)

JSON Representation of this class to save it to a json file.

Here is the call graph for this function:

◆ __repr__()

def __repr__ (   self)

◆ __str__()

def __str__ (   self)

◆ has_same_performance()

def has_same_performance (   self,
"MemoryInstance"  other 
)

Wether using this instance will result in the same estimations as using the other instance.

This method differs from eq since it does not consider e.g. the shared_memory_group_id

◆ update_size()

None update_size (   self,
int  new_size 
)

Update the memory size of this instance.

Member Data Documentation

◆ area

area

◆ double_buffering_support

double_buffering_support

◆ latency

latency

◆ name

name

◆ ports

ports

◆ r_cost

r_cost

◆ shared_memory_group_id

shared_memory_group_id

◆ size

size

◆ w_cost

w_cost

The documentation for this class was generated from the following file: