ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
|
This is the complete list of members for MemoryInstance, including all inherited members.
__eq__(self, object other) | MemoryInstance | |
__hash__(self) | MemoryInstance | |
__init__(self, str name, int size, float r_cost=0, float w_cost=0, float area=0, int r_port=1, int w_port=1, int rw_port=0, int latency=1, tuple[MemoryPort,...] ports=tuple(), str mem_type="sram", bool auto_cost_extraction=False, bool double_buffering_support=False, int shared_memory_group_id=-1) | MemoryInstance | |
__jsonrepr__(self) | MemoryInstance | |
__repr__(self) | MemoryInstance | |
__str__(self) | MemoryInstance | |
area | MemoryInstance | |
double_buffering_support | MemoryInstance | |
has_same_performance(self, "MemoryInstance" other) | MemoryInstance | |
latency | MemoryInstance | |
name | MemoryInstance | |
ports | MemoryInstance | |
r_cost | MemoryInstance | |
shared_memory_group_id | MemoryInstance | |
size | MemoryInstance | |
update_size(self, int new_size) | MemoryInstance | |
w_cost | MemoryInstance |