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ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
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Classes | |
| class | CactiConfig |
| Configuration for Cacti. More... | |
Functions | |
| tuple[float, float, float, float] | get_cacti_cost (str cacti_path, float tech_node, str mem_type, float mem_size_in_byte, float bw, str hd_hash="a") |
| extract time, area, r_energy, w_energy cost from cacti 7.0 :param cacti_path: the location of cacti :param tech_node: technology node (directly supported node by CACTI: 0.022, 0.032, 0.045, 0.065, 0.09, 0.18) :param mem_type: memory type (sram or dram) :param mem_size_in_byte: memory size (unit: byte) :param bw: memory IO bitwidth :param hd_hash: input file suffix when generating CACTI input file (useful and in avoid of file conflict for multi-processing simulation) Attention: for CACTI, the minimum mem_size=64B, minimum_rows=32 More... | |
| float | get_w_cost_per_weight_from_cacti (str cacti_path, dict[str, float] tech_param, dict[str, Any] hd_param, dict[str, Any] dimensions) |
| tuple[float, float, float, float] architecture.get_cacti_cost.get_cacti_cost | ( | str | cacti_path, |
| float | tech_node, | ||
| str | mem_type, | ||
| float | mem_size_in_byte, | ||
| float | bw, | ||
| str | hd_hash = "a" |
||
| ) |
extract time, area, r_energy, w_energy cost from cacti 7.0 :param cacti_path: the location of cacti :param tech_node: technology node (directly supported node by CACTI: 0.022, 0.032, 0.045, 0.065, 0.09, 0.18) :param mem_type: memory type (sram or dram) :param mem_size_in_byte: memory size (unit: byte) :param bw: memory IO bitwidth :param hd_hash: input file suffix when generating CACTI input file (useful and in avoid of file conflict for multi-processing simulation) Attention: for CACTI, the minimum mem_size=64B, minimum_rows=32

| float architecture.get_cacti_cost.get_w_cost_per_weight_from_cacti | ( | str | cacti_path, |
| dict[str, float] | tech_param, | ||
| dict[str, Any] | hd_param, | ||
| dict[str, Any] | dimensions | ||
| ) |
