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ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
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Classes | |
| class | SearchInterLayerDataLocalityStage |
| Class for searching lowest allowed memory level per operand per layer. More... | |
| class | ExploitInterLayerDataLocalityStage |
| This stage must be processed behind WorkloadStage. More... | |
Namespaces | |
| zigzag.stages.exploit_data_locality_stages | |
| ZigZag simulates a workload layer-by-layer. | |
Variables | |
| logger = logging.getLogger(__name__) | |