ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
NoValidLoopOrderingFoundException Class Reference

Indicates that not a single valid temporal loop was found. More...

Inheritance diagram for NoValidLoopOrderingFoundException:
Collaboration diagram for NoValidLoopOrderingFoundException:

Detailed Description

Indicates that not a single valid temporal loop was found.


The documentation for this class was generated from the following file: