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1.9.1
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ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
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This is the complete list of members for TemporalMapping, including all inherited members.
| __init__(self, TemporalMappingDict temporal_mapping_dict, LayerNode layer_node, TemporalMappingType mapping_type) | TemporalMapping | |
| __jsonrepr__(self) | TemporalMapping | |
| __repr__(self) | TemporalMapping | |
| __str__(self) | TemporalMapping | |
| calc_cycle_cabl_level(self) | TemporalMapping | |
| calc_top_r_and_ir_loop(self) | TemporalMapping | |
| cycle_cabl_level | TemporalMapping | |
| innermost_stationary_loop_merge_down(self) | TemporalMapping | |
| layer_node | TemporalMapping | |
| mac_level_data_stationary_cycle | TemporalMapping | |
| mapping_dic_origin | TemporalMapping | |
| mapping_dic_stationary | TemporalMapping | |
| mem_level | TemporalMapping | |
| operand_list | TemporalMapping | |
| top_ir_loop_size | TemporalMapping | |
| top_r_loop_size | TemporalMapping | |
| total_cycle | TemporalMapping | |
| type | TemporalMapping |
1.9.1