ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
Mapping Member List

This is the complete list of members for Mapping, including all inherited members.

__init__(self, Accelerator accelerator, SpatialMappingPerMemLvl|SpatialMappingInternal spatial_mapping, TemporalMapping temporal_mapping, LayerNode layer_node, bool access_same_data_considered_as_no_access=False)Mapping
acceleratorMapping
access_same_data_considered_as_no_accessMapping
calc_data_access(self)Mapping
calc_data_size(self)Mapping
calc_effective_data_size(self)Mapping
calc_req_mem_bw_and_data_transfer_rate(self)Mapping
combine_spatial_temporal_mapping_dict(self)Mapping
combined_mapping_dict_1s1tMapping
combined_mapping_dict_1s1t_reformMapping
combined_mapping_dict_1s2tMapping
combined_mapping_dict_1s2t_reformMapping
data_access_rawMapping
data_access_raw2Mapping
data_bit_per_levelMapping
data_bit_per_level_unrolledMapping
data_elem_per_levelMapping
data_elem_per_level_unrolledMapping
data_precision_dictMapping
disable_data_traffic_external(self)Mapping
effective_data_bitMapping
effective_data_elemMapping
gen_data_precision_dict(self)Mapping
gen_r_ir_loop_list(self)Mapping
get_psum_flags(self)Mapping
ir_loop_size_cablMapping
ir_loop_size_cabl2Mapping
ir_loop_size_per_levelMapping
layer_nodeMapping
mem_levelMapping
operand_listMapping
output_ir_loop_size_caalMapping
psum_flagMapping
r_loop_size_cablMapping
r_loop_size_cabl2Mapping
r_loop_size_per_levelMapping
r_loop_size_per_level2Mapping
spatial_mappingMapping
temporal_mappingMapping