ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
PortActivity Member List

This is the complete list of members for PortActivity, including all inherited members.

__hash__(self)PortActivity
__init__(self, int real_cycle, int allowed_cycle, int period, int period_count, LayerOperand layer_op, int mem_lv, DataDirection mov_dir)PortActivity
__repr__(self)PortActivity
__str__(self)PortActivity
allowed_cyclePortActivity
mem_updating_windowPortActivity
periodPortActivity
period_countPortActivity
real_cyclePortActivity
stall_or_slackPortActivity
stall_or_slack_per_periodPortActivity