ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
MinimalLatencyStage Member List

This is the complete list of members for MinimalLatencyStage, including all inherited members.

__init__(self, list[StageCallable] list_of_callables, *bool reduce_minimal_keep_others=False, **Any kwargs)MinimalLatencyStage
zigzag::stages::stage::Stage.__init__(self, list["StageCallable"] list_of_callables, **Any kwargs)Stage
__iter__(self)Stage
is_leaf(self)Stage
keep_othersMinimalLatencyStage
kwargsStage
list_of_callablesStage
run(self)MinimalLatencyStage