ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
CactiParser Member List

This is the complete list of members for CactiParser, including all inherited members.

__init__(self)CactiParser
cacti_pathCactiParserstatic
CACTI_TOP_PATHCactiParserstatic
create_item(self, str mem_type, int size, int r_bw, int r_port, int w_port, int rw_port, int bank, float technology=0.022, str mem_pool_path=MEM_POOL_PATH, str cacti_top_path=CACTI_TOP_PATH)CactiParser
get_item(self, *str mem_name, str mem_type, int size, int r_bw, int r_port, int w_port, int rw_port, int bank, float technology=0.022, str mem_pool_path=MEM_POOL_PATH, str cacti_top_path=CACTI_TOP_PATH)CactiParser
item_exists(self, int size, int r_bw, int r_port, int w_port, int rw_port, int bank, float technology, str mem_pool_path=MEM_POOL_PATH)CactiParser
MEM_POOL_PATHCactiParserstatic