ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
MemoryLevel Member List

This is the complete list of members for MemoryLevel, including all inherited members.

__eq__(self, Any other)MemoryLevel
__hash__(self)MemoryLevel
__init__(self, MemoryInstance memory_instance, list[MemoryOperand] operands, dict[MemoryOperand, int] mem_level_of_operands, PortAllocation port_alloc, ServedMemDimensions served_dimensions, OperationalArrayABC operational_array, int identifier)MemoryLevel
__jsonrepr__(self)MemoryLevel
__repr__(self)MemoryLevel
__str__(self)MemoryLevel
bandwidths_maxMemoryLevel
bandwidths_minMemoryLevel
formatted_stringMemoryLevel
get_max_bandwidth(self, MemoryOperand operand, DataDirection data_dir)MemoryLevel
get_min_bandwidth(self, MemoryOperand operand, DataDirection data_dir)MemoryLevel
has_same_performance(self, "MemoryLevel" other)MemoryLevel
idMemoryLevel
mem_level_of_operandsMemoryLevel
memory_instanceMemoryLevel
nameMemoryLevel
oa_dim_sizesMemoryLevel
operandsMemoryLevel
port_alloc_rawMemoryLevel
portsMemoryLevel
read_energyMemoryLevel
served_dimensionsMemoryLevel
unroll_count(self)MemoryLevel
write_energyMemoryLevel