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1.9.1
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ZigZag - Deep Learning Hardware Design Space Exploration
This repository presents the novel version of our tried-and-tested hardware Architecture-Mapping Design Space Exploration (DSE) Framework for Deep Learning (DL) accelerators. ZigZag bridges the gap between algorithmic DL decisions and their acceleration cost on specialized accelerators through a fast and accurate hardware cost estimation.
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This is the complete list of members for Accelerator, including all inherited members.
| __eq__(self, object other) | Accelerator | |
| __hash__(self) | Accelerator | |
| __init__(self, int core_id, str name, OperationalArrayABC operational_array, MemoryHierarchy memory_hierarchy, SpatialMapping|None dataflows=None) | Accelerator | |
| __jsonrepr__(self) | Accelerator | |
| __repr__(self) | Accelerator | |
| __str__(self) | Accelerator | |
| dataflows | Accelerator | |
| get_memory_bw_dict(self) | Accelerator | |
| get_memory_bw_min_dict(self) | Accelerator | |
| get_memory_level(self, MemoryOperand mem_op, int mem_lv) | Accelerator | |
| get_top_memory_instance(self, MemoryOperand mem_op) | Accelerator | |
| has_same_performance(self, "Accelerator" other) | Accelerator | |
| id | Accelerator | |
| mem_hierarchy_dict | Accelerator | |
| mem_r_bw_dict | Accelerator | |
| mem_r_bw_min_dict | Accelerator | |
| mem_sharing_list | Accelerator | |
| mem_size_dict | Accelerator | |
| mem_w_bw_dict | Accelerator | |
| mem_w_bw_min_dict | Accelerator | |
| memory_hierarchy | Accelerator | |
| name | Accelerator | |
| operational_array | Accelerator | |
| recalculate_memory_hierarchy_information(self) | Accelerator |
1.9.1